C Programming Language :: Cache Analysis


	Cache Analysis Hi. I had implemented PREFETCH (PREF @R1) insn and it's perfectly generating instructions within the assembly code. Generation of prefetch opcode value matches with objdump generated opcode and simulator generated opcode. The simulator can't cross verify the content of CACHE after data is sent from register R1 to cache. GDB (v-6.6) doesn't have support to verify cache content. I had build the insn on GCC(v4.3) and cross-compiled for one of the RISC based architecture. How can I cross-verify the cache content? BR Mukesh K Srivastava In article <1180871289.126881.195@x35g2000prf.googlegroups.com>, srimk@gmail.com <srimk@gmail.com> wrote: >I had implemented PREFETCH (PREF @R1) insn and it's perfectly >generating instructions within the assembly code. Prefetch, assembly code, cache, odump, simulators, debuggers -- none of these things are defined by the C language. All of them are system specific. You will need to ask in a newsgroup that deals with your particular system or tool chain. Do not, by the way, be surprised if it turns out that the answer is "All you can do is put on a hardware probe." -- Okay, buzzwords only. Two syllables, tops. -- Laurie Anderson